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Contact Simon if you want to use the system. You should have knowledge of radio frequency technology and regulations. There will be a test.
- Direct Quadrature Receiver/Transmitter
- Separate LOs for receive and transmit paths
- 55 MHz IF lowpass filter
- 2x125 MSa/s 12 bit ADCs
- Altera EP4CGX22C FPGA with DSP core
- 2x250 MSa/s 16 bit DACs
Rewriting the FPGA firmware
The factory firmware has several drawbacks that make it difficult to use the system easily:
- Decimation is done in 5 stages, each halving the sample rate. This leads to an awful lot of digital filter noise, and decimation 32 is not really sufficient for most applications.
* New design using a 2x16 multiplier FIR filter with symmetry handling and accumulator (i.e. 31 coefficients in a symmetric lowpass filter design without decimation) * Additional fixed IIR filters implementing high decimation factors
- Table based NCO. This takes up lots of FPGA space, and has limited accuracy.